Introduction

In the previous units, we have discussed the instruction set, register organization and pipelining, and control unit organization. The trend of those years was to have a large instruction set, a large number of addressing modes and about 16 -32 registers. However, their existed a pool of thought which was in favor of having simplicity in instruction set. This logic was mainly based on the type of the programs, which were being written for various machines. This led to the development of a new type of computers called Reduced Instruction Set Computer (RISC). In this unit, we will discuss about the RISC machines. Our emphasis will be on discussing the basic principles of FUSC and its pipeline. We will also discuss the arithmetic and logic units here. 

Objectives

After going through this unit you should be able to:

• define why complexity of instruction increased?
• describe the reasons for developing RISC;
• define the basic design principles of RISC;
• describe the importance of having large register file;
• discuss some of the common comments about RISC;
• describe FUSC pipelining; and
• define the optimisation in RISC pipelining